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Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator ADCMP609
FEATURES
Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage 40 ns propagation delay Low power 1 mW at 2.5 V Shutdown pin Programmable hysteresis Power supply rejection > 60 dB -40C to +125C operation
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING INPUT +
ADCMP609
INVERTING INPUT -
Q OUTPUT
SDN
Figure 1.
APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators
GENERAL DESCRIPTION
The ADCMP609 is a fast comparator fabricated on XFCB2, an Analog Devices, Inc. proprietary process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE - 0.2 V to VCC + 0.2 V, low noise, TTL-/ CMOS-compatible output drivers, and adjustable hysteresis and/or shutdown inputs. The device offers 40 ns propagation delay driving a 15 pF load with 10 mV overdrive on 500 A typical supply current. A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a -0.2 V to +3.0 V input signal range up to a +5.5 V positive supply with a -0.2 V to +5.7 V input signal range. The TTL-/CMOS-compatible output stage is designed to drive up to 15 pF with full rated timing specifications and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator's input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. A programmable hysteresis features is also provided. The ADCMP609, available in an 8-lead MSOP package, features a shutdown pin and hysteresis control.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06918-001
ADCMP609 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 4 Thermal Resistance ...................................................................... 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Application Information...................................................................8 Power/Ground Layout and Bypassing........................................8 TTL-/CMOS-Compatible Output Stage ....................................8 Optimizing Performance..............................................................8 Comparator PropagationDelay Dispersion ...............................8 Comparator Hysteresis .................................................................9 Crossover Bias Point .................................................................. 10 Minimum Input Slew Rate Requirement ................................ 10 Typical Application Circuits ......................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12
REVISION HISTORY
7/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADCMP609 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 2.5 V, TA = -40 C to +125 C; typical value is TA = 25C, unless otherwise noted. Table 1.
Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Symbol VP, VN Conditions VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Min -0.2 -0.2 -5.0 -0.4 -1.0 -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V AV CMRR VCC = 2.5 V VCM = -0.2 V to +2.7 V VCC = 5.5 V RHYS = Current -1 A Hysteresis = 120 mV Comparator is operating Shutdown guaranteed VIH = VCC lCC < 100 A VPP = 10 mV, output valid VCC = 2.5 V to 5.5 V IOH = 0.8 mA, VCC = 2.5 V IOL = 0.8 mA, VCC = 2.5 V VCC = 2.5 V to 5.5 V 10% to 90%, VCC = 2.5 V 10% to 90%, VCC = 5.5 V VOD = 10 mV, VCC = 2.5 V VOD = 50 mV, VCC = 5.5 V VCC = 2.5 V VCC = 5.5 V VCC = 2.5 V VCC = 5.5 V 10 mV < VOD < 125 mV -0.2 V < VCM < VCC + 0.2 V 200 100 80 50 50 0.1 1.145 30 2.0 -0.2 -6 1.25 1.35 120 VCC +0.4 +6 3 Typ Max VCC + 0.2 V VCC + 0.2 V VCC +5.0 +0.4 +1.0 7000 4000 Unit V V V mV A A pF k k dB dB dB mV V k V V A ns ns V V ns ns ns ns ns ns ns ns ns ns 5.5 650 1100 1.7 7 260 V A A mW mW dB A
VOS IP, IN CP, CN
1
Hysteresis HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value SHUTDOWN PIN CHARACTERISTICS1 VIH VIL IIH Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level AC PERFORMANCE2 Rise Time/Fall Time Propagation Delay Propagation Delay Skew--Rising to Falling Transition Propagation Delay Skew--Q to QB Overdrive Dispersion Common-Mode Dispersion POWER SUPPLY Supply Voltage Range Positive Supply Current Power Dissipation Power Supply Rejection Ratio Shutdown Current
1
+0.4 300 150
tSD tH VOH VOL tR/tF tPD
VCC - 0.4 0.4 25 to 50 45 to 75 30 to 50 35 to 60 4.5 8 3 4 12 1.5 2.5
VCC IVCC PD PSRR ISD
VCC = 2.5 V VCC = 5.5 V VCC = 2.5 V VCC = 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V
550 800 1.4 4.5 -50 150
The output is a high impedance mode when the device is in shutdown mode. Note that this feature should be used with care since the enable/disable time is much longer than with a true tristate output. 2 VIN = 100 mV square input at 1 MHz, VCM = 0 V, CL = 15 pF, VCCI = 2.5 V, unless otherwise noted.
Rev. 0 | Page 3 of 12
ADCMP609 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltages Supply Voltage (VCC to GND) Supply Differential Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (SDN to GND) Maximum Input/Output Current Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Operating Temperature Ambient Temperature Junction Temperature Rating -0.5 V to +6.0 V -6.0 V to +6.0 V -0.5 V to VCC + 0.5 V (VCC + 0.5 V) 50 mA -0.5 V to VCC + 0.5 V 50 mA -0.5 V to VCC + 0.5 V 50 mA 50 mA -40C to +125C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3.
Package Type ADCMP609 8-Lead MSOP
1
JA1 130
Unit C/W
Measurement in still air.
ESD CAUTION
Rev. 0 | Page 4 of 12
ADCMP609 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC 1 VP 2 VN 3 SDN 4
8
Q Q
06918-002
ADCMP609
TOP VIEW (Not to Scale)
7 6 5
VEE HYS
Figure 2. ADCMP609 Pin Configuration
Table 4. ADCMP609 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VCC VP VN SDN HYS VEE Q Q Description VCC Supply. Noninverting Analog Input. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Hysteresis Control. Bias with resistor or current source for hysteresis. Negative Supply Voltage. Noninverting Output. Q is at logic low if the analog voltage at the noninverting input (VP) is greater than the analog voltage at the inverting input (VN) provided the comparator is in compare mode. Inverting Output. Q is at logic high if the analog voltage at the noninverting input (VP) is greater than the analog voltage at the inverting input (VN) provided the comparator is in compare mode.
Rev. 0 | Page 5 of 12
ADCMP609 TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 2.5 V, TA = 25C, unless otherwise noted.
400 300 200 100 0 -100 -200
06918-003
160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0
VCC = 5.5 VCC = 2.5
-400 -1
0
1
2
3
4
5
6
7
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 HYS RESISTOR (k)
HYS PIN VOLTAGE (V)
Figure 3. HYS Pin Current (A) vs. Voltage (V)
Figure 6. Hysteresis vs. HYS Resistor
5 4 3
1.5 SOURCE 1.0 SINK
1
IB (A)
LOAD CURRENT (mA)
2
0.5
0 -1 -2 -3 -4 -5 -1.0 +125C +25C
06918-004
0
-0.5
06918-007
-40C -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
-1.0 -1.0 -0.5
0
0.5
1.0
1.5
VOUT (V)
2.0
2.5
3.0
3.5
4.0
VCM AT VCC (2.5V)
Figure 4. Input Bias Current vs. Input Common-Mode Voltage (V)
Figure 7. VOH/VOL vs. Load Current (mA)
60 55 50 45
38.0 37.8
PROPAGATION DELAY (ns)
37.6 37.4 37.2 37.0 36.8 36.6 36.4
PROPAGATION DELAY FALL
TPD (ns)
40 35 30 25 20
VCC = 2.5V RISE DELAY
VCC = 5.5V RISE DELAY VCC = 5.5V FALL DELAY VCC = 2.5V FALL DELAY
06918-005
PROPAGATION DELAY RISE
36.2 36.0 0.5 1.0 1.5 2.0 2.5 3.0
0
50 OD (mV)
100
150
VCM AT VCC (2.5V)
Figure 5. Propagation Delay vs. Input Overdrive at VCC = 2.5 V and 5.5 V
Figure 8. Propagation Delay vs. Input Common-Mode Voltage (V)
Rev. 0 | Page 6 of 12
06918-008
06918-006
-300
HYSTERESIS (mV)
VCC = 2.5V
VCC = 5.5V
CURRENT (A)
ADCMP609
Q
Q
Q
Q
06918-009
0.5V/DIV
10ns/DIV
1V/DIV
10ns/DIV
Figure 9. 1 MHz Output Voltage Waveform at VCC = 2.5 V
Figure 10. 1 MHz Output Voltage Waveform at VCC = 5.5 V
Rev. 0 | Page 7 of 12
06918-010
ADCMP609 APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP609 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCC) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. A 0.1 F bypass capacitor should be placed as close as possible to each VCC supply pin. The capacitor should be connected to the GND plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (Figure 11). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads.
VLOGIC
A1
Q1
+IN -IN AV
OUTPUT
A2
Q2
06918-011
GAIN STAGE
OUTPUT STAGE
Figure 11. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, common power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Higher impedances encourage undesired coupling.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The outputs of the ADCMP609 are designed to directly drive one Schottky TTL or three low power Schottky TTL loads (or an equivalent). For large fan outputs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. With the rated 15 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time. Because of this, the total propagation delay decreases as VCC decreases, and instability in the power supply may appear as excess delay dispersion. Delay is measured to the 50% point for whatever supply is in use; thus, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP609 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mV to VCC - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold).
Rev. 0 | Page 8 of 12
ADCMP609
Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (see Figure 12 and Figure 13). ADCMP609 dispersion is typically <12 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negative-going inputs, and very low output skews. Remember to add the actual device offset to the overdrive for repeatable dispersion measurements.
500mV OVERDRIVE
OUTPUT
VOH
VOL
-VH 2
0
+VH 2
Figure 14. Comparator Hysteresis Transfer Function
INPUT VOLTAGE 10mV OVERDRIVE VN VOS
The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and can even induce oscillation in some cases. The ADCMP609 comparator offers a programmable hysteresis feature that significantly improves accuracy and stability. Connecting an external pull-down resistor or a current source from the HYS pin to GND varies the amount of hysteresis in a predictable, stable manner. Leaving the HYS pin disconnected or driving it high removes the hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 15 illustrates the amount of hysteresis applied as a function of the external resistor value.
160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 VCC = 5.5 VCC = 2.5
Q/Q OUTPUT
Figure 12. Propagation Delay--Overdrive Dispersion
INPUT VOLTAGE 1V/ns VN VOS 10V/ns
06918-012
DISPERSION
Q/Q OUTPUT
Figure 13. Propagation Delay--Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 14. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2. The new switching threshold becomes -VH/2. The comparator remains in the high state until the threshold, -VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2.
06918-013
DISPERSION
HYSTERESIS (mV)
06918-014
INPUT
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 HYS RESISTOR (k)
Figure 15. Hysteresis vs. HYS Resistor
The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7 k 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it impairs the latch function and often degrades the jitter performance of the device.
Rev. 0 | Page 9 of 12
06918-006
ADCMP609
With the pin driven low, hysteresis may become large, but in this device, the effect is not reliable or intended as a latch function.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PC board design practice (as discussed in the Optimizing Performance section), these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation may be encountered. These oscillations are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and PC board. In many applications, chattering is not harmful.
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. The ADCMP609 slightly elaborates on this scheme. Crossover points can be found at approximately 0.8 V and 1.6 V.
Rev. 0 | Page 10 of 12
ADCMP609 TYPICAL APPLICATION CIRCUITS
5V 20k 39k
ADCMP609
39k 470pF HYS
OUTPUT
150k
150k
Figure 16. Voltage-Controlled Oscillator
5V
INPUT
10k
+ OUTPUT -
06918-017
ADCMP609
VREF 0.1F HYS
0.02F 10k
Figure 17. Duty Cycle to Differential Voltage Converter
2.5V
ADCMP608
INPUT 1.25V 50mV
CMOS PWM OUTPUT
INPUT 1.25V REF
10k 10k
ADCMP609
10k 220pF HYS
06918-018
100k
Figure 18. Oscillator and Pulse Width Modulator
Rev. 0 | Page 11 of 12
06918-016
CONTROL VOLTAGE 0V TO 2.5V
ADCMP609 OUTLINE DIMENSIONS
3.20 3.00 2.80
3.20 3.00 2.80 PIN 1
8
5
1
5.15 4.90 4.65
4
0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure19. 8-Lead Mini Small Outline Package (MSOP) (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model ADCMP609BRMZ 1 ADCMP609BRMZ-REEL1 ADCMP609BRMZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP)
Package Option RM-8 RM-8 RM-8
Branding GW GW GW
Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06918-0-7/07(0)
Rev. 0 | Page 12 of 12

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